1. Field of the Invention
The present invention relates to synchronous semiconductor memory devices, and more particularly, to a synchronous semiconductor memory device which strobes external signals including a control signal, an address signal and a data signal in synchronization with an external clock signal.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as a "DRAM") which is employed as a main memory cannot follow a microprocessor (hereinafter referred to as an "MPU") in operating speed although its operation has been speeded up. Therefore, it is frequently pointed out that an access time and a cycle time of such a DRAM bottleneck the operation of the overall system, to deteriorate its performance. It has been proposed in recent years to employ as a main memory for a high speed MPU a synchronous DRAM (hereinafter referred to as an "SDRAM") which operates in synchronization with a clock signal. Takai et al. read a paper on an SDRAM of pipeline operation carrying out writing of data on a bit basis (Symposium on VLSI circuit, 1993), and Choi et al. read a paper on an SDRAM of 2-bit prefetch carrying out writing of data on a 2-bit basis (Symposium on VLSI circuit, 1993). Description will be given hereinafter of the SDRAM of pipeline operation and the SDRAM of 2-bit prefetch.
FIG. 19 is a block diagram functionally showing a structure of a main part in a conventional SDRAM of pipeline operation. FIG. 19 shows a structure of a functional portion which is related to 1-bit data input/output of the SDRAM having a by 8-bit structure. An array part which is related to a data input/output terminal DQi includes memory arrays 51a and 51b forming banks #1 and #2 respectively.
With respect to memory array 51a forming bank #1, there is provided an X decoder group 52a including a plurality of row decoders for decoding address signals X0 to Xj and selecting a corresponding row of memory array 51a, a Y decoder group 53a including a plurality of column decoders for decoding column address signals Y3 to Yk and generating column selection signals selecting corresponding columns of memory array 51a, and a sense amplifier group 54a for detecting and amplifying data of memory cells which are connected to the selected row of memory array 51a.
X decoder group 52a includes the row decoders which are provided in correspondence to respective word lines of memory array 51a. Row decoders are selected in accordance with address signals X0 to Xj, so that the word lines provided for the selected row decoders are selected.
Y decoder group 53a includes the column decoders which are provided for the respective column selection lines of memory array 51a. A single column selection line brings eight pairs of bit lines into selected states. X decoder group 52a and Y decoder group 53a simultaneously bring 8-bit memory cells into selected states in memory array 51a. X decoder group 52a and Y decoder group 53a are both activated by a bank specifying signal B1.
Bank #1 is further provided with a bus GIO as internal data transmission lines (global IO lines) for transmitting data which are detected and amplified by sense amplifier group 54a and transmitting write data to selected memory cells of memory array 51a. Global IO line bus GIO includes eight pairs of global IO lines for simultaneously transferring and receiving data to and from simultaneously selected 8-bit memory cells.
In order to read data, bank #1 is provided with a preamplifier group 55a which is activated in response to a preamplifier activation signal .phi.PA1 for amplifying data on global IO line bus GIO, a read register 56a for storing data amplified in preamplifier group 55a, and an output buffer 57a for successively outputting the data stored in read register 56a.
Each of preamplifier group 55a and read register 56a has a structure of an 8-bit width in correspondence to the eight pairs of global IO lines. Read register 56a latches the data outputted from preamplifier group 55a to successively output the same in response to a register activation signal .phi.Rr1.
Output buffer 57a transmits the 8-bit data successively outputted from read register 56a to data input/output terminal DQi in response to an output enable signal .phi.OE1. Referring to FIG. 19, data input/output terminal DQi is adapted to input and output the data. Alternatively, the data may be inputted and outputted through separate terminals.
In order to write data, on the other hand, bank #1 is further provided with an input buffer 58a of a 1-bit width which is activated in response to an input buffer activation signal .phi.DB1 for generating internal write data from input data supplied to data input/output terminal DQi, a write register 59a which is activated in response to a register activation signal .phi.Rw1 for successively storing write data received from input buffer 58a (in accordance with wrap addresses), a write buffer group 60a which is activated in response to a write buffer activation signal .phi.WB1 for amplifying and transmitting the data stored in write register 59a to global IO line bus GIO, and an equalize circuit group 61a equalizing global IO line pair bus G10.
Each of write buffer group 60a and write register 59a has an 8-bit width.
Similarly to the above, bank #2 includes memory array 51b, an X decoder group 52b, a Y decoder group 53b, a sense amplifier group 54b which is activated in response to a sense amplifier activation signal .phi.SA2, a preamplifier group 55b which is activated in response to a preamplifier activation signal .phi.PA2, a read register 56b which is activated in response to a register activation signal .phi.Rr2, an output buffer 57b which is activated in response to an output enable signal .phi.OE2, an equalize circuit group 61b which is activated in response to an equalize circuit activation signal .phi.EQ2, a write buffer group 60b which is activated in response to a buffer activation signal .phi.WB2, a write register 59b which is activated in response to a register activation signal .phi.Rw2, and an input buffer 58b which is activated in response to a buffer activation signal .phi.DB2.
Banks #1 and #2 are identical in structure to each other. Due to read registers 56a and 56b and write registers 59a and 59b, it is possible to input/output data in synchronization with a high-speed clock signal through a single data input/output terminal DQi.
As to control signals for banks #1 and #2, only those for either bank are generated in accordance with a bank specifying signal B1 or B2.
A functional block 300 shown in FIG. 19 is provided for each data input/output terminal. The SDRAM of the by 8-bit structure includes eight such functional blocks 300.
Since banks #1 and #2 are substantially identical in structure to each other, it is possible to drive banks #1 and #2 substantially independently of each other by activating only one of these banks by bank specifying signal B1 or B2.
Further, banks #1 and #2 are respectively provided with data read registers 56a and 56b and data write registers 59a and 59b independently of each other, whereby it is possible to correctly read and write data with no collision in switching between data read and write operation modes as well as in switching between banks #1 and #2.
First and second control signal generation circuits 62 and 63 and a clock counter 64 are provided as control systems for independently driving banks #1 and #2 respectively.
First control signal generation circuit 62 takes in externally applied control signals, i.e., an external row address strobe signal ext./RAS ("1" before reference characters indicating signals indicates that the signal is active at a low level in the specification and the drawings), an external column address strobe signal ext./CAS, an external output enable signal ext./OE, an external write enable signal (write authorization signal) ext./WE and a mask command signal WM in synchronization with an external clock signal CLK which is a system clock, for example, to generate internal control signals .phi.xa, .phi.ya, .phi.W, .phi.O, .phi.R and .phi.C.
Second control signal generation circuit 63 generates control signals for independently driving banks #1 and #2 respectively, i.e., equalize circuit activation signals .phi.EQ1 and .phi.EQ2, sense amplifier activation signals .phi.SA1 and .phi.SA2, preamplifier activation signals .phi.PA1 and .phi.PA2, write buffer activation signals .phi.WB1 and .phi.WB2, input buffer activation signals .phi.DB1 and .phi.DB2, and output buffer activation signals .phi.OE1 and .phi.OE2 in response to bank specifying signals B1 and B2, internal control signals .phi.W, .phi.O, .phi.R and .phi.C, and the output of clock counter 64.
The SDRAM further includes, as peripheral circuits, an X address buffer 65 which takes in external address signals ext./A0 to ext./Ai in response to internal control signal .phi.xa to generate internal address signals X0 to Xj and bank selection signals B1 and B2, a Y address buffer 66 which is activated in response to internal control signal .phi.ya for generating column selection signals Y3 to Yk for specifying column selection lines, wrap address bits Y0 to Y2 for specifying a first bit line pair (column) in a continuous access operation, and bank specifying signals B1 and B2, and a register control circuit 67 which generates wrap addresses WY0 to WY7, register activation signals .phi.Rr1 and .phi.Rr2 for controlling read registers 56a and 56b, and register activation signals .phi.Rw1 and .phi.Rw2 for driving write registers 59a and 59b.
Register control circuit 67 is supplied with bank specifying signal B1 or B2, to generate the register driving signal for only the selected bank.
FIG. 20 illustrates a chip layout of the conventional SDRAM. This figure shows a chip layout of a 16-megabit SDRAM having a 2 M word by 8 bit structure as an example.
The SDRAM includes four memory mats MM1 to MM4, each having 4-megabit storage capacity. Each of memory mats MM1 to MM4 includes 16 memory arrays MA1 to MA16 each having 256-K bit storage capacity.
Row decoders RD1 to RD4 are arranged on respective one sides of memory mats MM1 to MM4 along chip longer sides. Further, column decoders CD1 to CD4 are arranged on chip center sides of memory mats MM1 to MM4 along shorter sides respectively. At the output end of column decoder CD (symbol CD is adapted to generically indicate column decoders CD1 to CD4), column selection lines CSL extending across the respective arrays of the corresponding memory mat MM (symbol MM generically indicates memory mats MM1 to MM4) are provided. Each column selection line CSL simultaneously brings four pairs of bit lines into selected states.
Global IO line pairs GIO for transmitting internal data are arranged across the respective arrays along the longer sides of memory mats MM1 to MM4 respectively.
The respective memory mats MM1 to MM4 are further provided on the chip center sides thereof with input/output circuits PW1 to PW4, which are each formed by a preamplifier PA for amplifying data read from selected memory cells and a write buffer WB for transmitting write data to the selected memory cells.
A peripheral circuit PH including circuits for generating address and control signals is arranged on the chip central portion.
The SDRAM shown in FIG. 20 includes two banks #1 and #2 which can carry out precharge operations and activating operations (word line selecting, and sense and column selecting operations) independently of each other, as shown in FIG. 19. Bank #1 includes memory mats MM1 and MM2, while bank #2 includes memory mats MM3 and MM4. The number of banks #1 and #2 is changeable.
Each of memory mats MM1 to MM4 includes two array blocks each having 2-megabit storage capacity. One of the array blocks is formed by memory arrays MA1 to MA8, while the other array block is formed by memory arrays MA9 to MA16. A single memory array is selected at the maximum in each array block.
Four memory arrays are simultaneously activated. In other words, a single memory array is selected from each array block of each memory mat in the selected bank. For example, memory arrays MA16 and MA7, MA15 and MA8, MA14 and MA5, MA13 and MA6, MA12 and MA13, MA11 and MA4, MA10 and MA1, and MA9 and MA2 are activated in pairs. In FIG. 18, memory arrays MA7 and MA16 of memory mats MM3 and MM4 are activated respectively.
On the other hand, two column selection lines CSL are simultaneously selected. Each column selection line CSL selects four pairs of bit lines. Thus, 2.times.4=8 bit memory cells are selected at one time.
Input/output circuits PW are employed in common for the respective memory arrays of the corresponding memory mats MM. Each input/output circuit PW includes four preamplifiers PA and four write buffers WB. Namely, the overall SDRAM includes 16(=4.times.4) preamplifiers PA and 16 write buffers WB.
Preamplifiers PA and write buffers WB (input/output circuits PW) which are collectively arranged on the chip central portion are driven by control circuits included in peripheral circuit PH. Thus, signal lines for controlling operations of preamplifiers PA and write buffers WB are reduced in length, whereby loads on the signal lines can be reduced to implement a high-speed operation.
Since peripheral circuit PH is collectively arranged on the chip central portion, data are inputted/outputted through the chip central portion, whereby the data input/output terminals are arranged on a package central portion as to pin arrangement in packaging. Therefore, distances between peripheral circuit PH and the data input/output terminals are reduced to enable high-speed input/output of data.
FIG. 21 illustrates arrangement of IO lines in the SDRAM shown in FIG. 20. This figure shows two 2-megabit memory arrays MSA1 and MSA2. One 2-megabit memory array MSA2 is a 2-megabit array block which is arranged in a position separated from the chip central portion, while the other 2-megabit memory array MSA1 is a 2-megabit array block which is close to the chip central portion.
Each of 2-megabit memory arrays MSA1 and MSA2 includes 64 32-K bit memory arrays MK arranged in eight rows and eight columns. Word line shunt regions WS are provided between the 32-K bit memory arrays MK which are adjacent to each other along the word lines WL. In an ordinary DRAM, low-resistance metal wires of aluminum or the like are arranged in parallel with word lines WL of polysilicon, and the former are electrically connected with the latter at prescribed intervals in order to reduce resistances of the word lines. Regions for connecting the polysilicon word lines and the low-resistance metal wires are called word line shunt regions. No bit lines, i.e., no memory cells are present in the word line shunt regions, since it is necessary to connect the polysilicon word lines which are present under bit lines BL with low-resistance metal wire layers which are present above the bit lines.
One global IO line pair GIO is arranged along the longer side of memory mat MM. One global IO line pair is arranged in each of three word line shunt regions WS2, WS4 and WS6 of seven word line shunt regions WS1 to WS7 shown in FIG. 21. Two global IO line pairs are used by one 2 M bit memory array MSA.
Local IO line pairs LIO are provided in order to connect global IO line pairs GIO with a selected 256-K bit memory array MA. Two local IO line pairs LIO in total are arranged for each 256-K bit memory array MA so that one pair is arranged on one side and another pair is arranged on the other side. These local IO line pairs LIO are shared by two 256-K bit memory arrays MA adjacent to each other.
Block selecting switches BS are arranged in order to connect global IO line pairs GIO with local IO line pairs LIO. These block selecting switches BS are arranged in an end portion of memory mat MM and three word line shunt regions WS2, WS4 and WS6.
As to column selection lines CSL for transmitting column selection signals from the column decoders, a single line is brought into a selected state in memory mat MM. The single column selection line CSL selects two bit line pairs BLP to connect the same to corresponding local IO line pairs LIO in 2-megabit memory array MSA2 which is far from the chip central portion, while selecting two bit line pairs BLP to connect the same to corresponding local IO line pairs LIO in 2-megabit memory array MSA1 which is close to the chip central portion.
Namely, the single column selection line CSL causes four bit line pairs BLP to be brought to selected states, to connect the same to four global IO line pairs GIO through local IO line pairs LIO. Two memory mats MM are selected and four bit line pairs BLP are selected in each memory mat MM, whereby eight bit line pairs BLP are selected in total so that 8-bit memory cells are simultaneously accessible in total.
FIG. 22 is a diagram showing a Z portion of FIG. 21 in an enlarged scale. Referring to FIG. 22, the memory array includes a so-called alternately arranged shared sense amplifier structure. More specifically, a local IO line pair LIO2 and a sense amplifier series SAC2 shared by memory arrays MK1 and MK2 are provided in a region between memory arrays MK1 and MK2. Sense amplifiers SA in sense amplifier series SAC2 are provided corresponding to bit line pairs BLP of even numbered order, for example, in memory arrays MK1 and MK2.
A local IO line pair LIO3 and a sense amplifier series SAC3 shared by memory arrays MK2 and MK3 are provided in a region between memory arrays MK2 and MK3. Sense amplifiers SA of sense amplifier series SAC2 are provided corresponding to bit line pairs BLP of odd numbered order, for example, in memory arrays MK2 and MK3.
When memory array MK2, for example, is selected, each sense amplifier SA in sense amplifier series SAC2 and SAC3 is connected to a corresponding bit line pair of memory array MK2. Sense amplifier SA corresponding to a selected column of sense amplifier series SAC2 is connected to local IO line pair LIO2, and further connected to global IO line pair GIO through block selecting switch BS. Sense amplifier SA corresponding to a selected column of sense amplifier series SAC3 is connected to local IO line pair LIO3, and further connected to global IO line pair GIO, not shown, through block selecting switch BS, not shown.
FIG. 23 illustrates a structure which is related to a single 32-K bit memory array MK2 with one part omitted. For simplification, only a portion which is related to local IO line pair LIO2 and sense amplifier series SAC2 in memory array MK2 is shown in FIG. 23. A portion which is related to local IO line pair LIO3 and sense amplifier series SAC3 is not shown.
Referring to FIG. 23, 32-K bit memory array MK2 includes word lines WL which receive row selection signals from the row decoders, bit line pairs BLP which are arranged in a direction intersecting with word lines WL, and dynamic memory cells MC which are arranged in correspondence to intersections between word lines WL and bit line pairs BLP.
Each memory cell MC includes an access transistor and a capacitor for storing information. Each bit line pair BLP includes bit lines BL and /BL which receive complementary signals. Referring to FIG. 23, memory cells MC are arranged in correspondence to intersections between bit lines BL and word lines WL.
An array selecting gate SAG1 is arranged at an end portion on the side of local IO line pair LIO2 of memory array MK1, not shown, and an array selecting gate SAG2 is arranged in an end portion on the side of local IO line pair LIO2 of memory array MK2. Array selecting gate SAG1 is rendered conductive in response to an array selection signal .phi.A1, and array selecting gate SAG2 is rendered conductive in response to an array selection signal .phi.A2. Bit line pairs BLP of memory arrays MK1 and MK2 are connected to sense amplifiers SA of sense amplifier series SAC2 through array selecting gates SAG1 and SAG2, respectively. Sense amplifiers SA are activated in response to a sense amplifier activation signal S0N.
A bit line equalize circuit EQB2 is provided to each sense amplifier SA for applying a precharge potential Vcc/2 to bit lines BL, /BL connected to the sense amplifier SA. Bit line equalize circuit EQB2 is activated in response to a bit line equalize signal BLEQ in a period before activation of sense amplifiers SA in data reading operation.
A column selecting gate CSG2 is provided to each sense amplifier SA for transmitting data sensed and amplified by the sense amplifier SA to local IO line pair LIO2. A local IO line pair equalize circuit EQL2 is provided for applying a precharge potential Vcc to local IO line pair LIO. Local IO line pair equalize circuit EQL2 is activated in response to a local IO line equalize signal LIOEQ during a period before activation of write buffers WB in data writing operation. Block selecting switches BS rendered conductive in response to a block selection signal .phi.B are provided between local IO line pair LIO2 and global IO line pair GIO.
The operation is now briefly stated. When memory array MK2 includes a selected word line WL, array selection signal .phi.A2 enters an active state so that bit line pairs BLP included in memory array MK2 are connected to sense amplifiers SA of sense amplifier series SAC2. An array selecting gate SAG1 which is provided for memory array MK1 enters a nonconductive state. Memory array MK1 maintains a precharged state.
In memory array MK2, memory cell data appear on the respective bit line pairs BLP, and thereafter sense amplifiers are activated to detect and amplify the memory cell data.
Then, the signal on column selection line CSL rises to a logical high or H level to enter an active state, whereby column selecting gate CSG2 conducts so that the data which are detected and amplified by sense amplifiers SA are transmitted to local IO line pair LIO2.
Subsequently or simultaneously, block selection signal .phi.B enters the H level in an active state, so that local IO line pair LIO2 is connected to global IO line pair GIO. In data reading, data of the global IO line pair are amplified through preamplifiers PA, to be stored in the read register and thereafter successively outputted. In data writing, on the other hand, write data which are supplied from write buffers WB are transmitted to the selected bit line pairs BLP through global IO line pairs GIO and local IO line pairs LIO, so that the data are written in the memory cells.
Block selection signals .phi.B enter active states only for memory array MK2 including the selected word line WL. This also applies to array selection signals .phi.A1 and .phi.A2. Block selection signal .phi.B and array selection signals .phi.A1 and .phi.A2 can be generated through a prescribed number of bits (four bits, for example) of row address signals.
FIG. 24 is a timing chart showing states of external signals when data of eight bits are read out continuously in such an SDRAM. The number of bits of data read out or written continuously is called burst length, which can be changed by a mode register in the SDRAM.
In the SDRAM, at the rising edge of external clock signal CLK which is a system clock, for example, an external control signal, external address signal Add, and the like are strobed. Address signal Add includes a row address signal X and a column address signal Y multiplexed in a time sharing manner.
At the rising edge of clock signal CLK in a cycle 1, if external row address strobe signal ext./RAS is at the L level in an active state, and external column address strobe signal ext./CAS and external write enable signal ext./WE are at the H level, address signal Add at that time is strobed as a row address signal Xa.
Then, at the rising edge of clock signal CLK in a cycle 4, if external column address strobe signal ext./CAS is at the L level in an active state, address signal Add at that time is strobed as a column address signal Yb. According to the strobed row address signal Xa and column address signal Yb, row and column selecting operations are carried out in the SDRAM. After a predetermined clock period (six clock cycles in FIG. 24) since external row address strobe signal ext./RAS fell to the L level, the first data b0 is outputted. In response to the falling of clock signal CLK, data b1 to b7 are outputted thereafter.
FIG. 25 is a timing chart showing states of external signals when data of eight bits are continuously written in the SDRAM.
In the writing operation, row address signal Xa is strobed similarly to the case of the data reading operation. More specifically, at the rising edge of clock signal CLK in the cycle 1, if signal ext./RAS is at the L level in an active state, and signals ext./CAS and ext./WE are at the H level, address signal Add at that time is strobed as row address signal Xa. At the rising edge of clock signal CLK in a cycle 3, if signals ext./CAS and ext./WE are both at the L level in an active state, column address signal Yb is strobed, and data b0 applied at that time is strobed as the first write data. In response to the rising edges of signals ext./RAS and ext./CAS, row and column selecting operations are carried out in the SDRAM. In synchronization with clock signals CLK, input data B1 to B7 are successively strobed. The input data are written in memory cells successively.
FIG. 26 is a circuit block diagram showing a specific structure of equalize circuit EQG and write buffer WB which are activated at the time of writing operation of the SDRAM. In FIG. 26, equalize circuit EQG and write buffer WB of bank #1 are shown.
Referring to FIG. 26, equalize circuit EQG includes N channel MOS transistors Tr1, Tr2 and Tr3. MOS transistor Tr1 has its source connected to global IO line GIOL, and receives power supply potential Vcc at its drain. MOS transistor Tr2 has its source connected to global IO line /GIOL, and receives power supply potential Vcc at its drain. MOS transistor Tr3 is connected between global IO lines GIOL and /GIOL. MOS transistors Tr1, Tr2 and Tr3 receive equalize circuit activation signal .phi.EQ1 at their gates.
Write buffer WB includes N channel MOS transistors Tr4, Tr5 and Tr6. MOS transistor Tr4 has its drain connected to global IO line GIOL, its source connected to a node N1, and its gate connected to one output node WRa of write transistor 59a. MOS transistor Tr5 has its drain connected to global IO line /GIOL, its source connected to node N1, and its gate connected to the other output node WRb of write transistor 59a. MOS transistor Tr6 has its drain connected to node N1, and its gate supplied with write buffer activation signal .phi.WB1.
FIG. 27 is a timing chart showing continuous writing operation (burst length=4) of the circuit shown in FIG. 26. Referring to FIGS. 26 and 27, operation of the circuit of FIG. 26 will be described. Signal .phi.EQ1 is brought to the H level in an active state in advance only for a prescribed time, so that MOS transistors Tr1, Tr2, and Tr3 of equalize circuit EQG are rendered conductive, and that global IO lines GIOL and /GIOL are charged to a prescribed potential Vcc-Vth (wherein Vth is a threshold voltage of an MOS transistor).
Signal /CAS attains the L level in an active state, and a continuous write command is given. In response to this, signal .phi.WB1 attains the H level in an active state. As a result, MOS transistor Tr6 of write buffer WB is rendered conductive. When write register 59a is activated in response to signal .phi.Rw1, and outputs the H level to one of two output nodes WRa and WRb in response to an externally applied data signal, MOS transistor Tr4 or Tr5 of write buffer WB is rendered conductive, causing global IO line GIOL or /GIOL to be grounded. The potential of global IO line pair GIO is written in memory cell MC of a desired address through the selected local IO line pair LIO and bit line pair BL.
Then, signal .phi.EQ1 attains the H level in an active state, and global IO line pair GIO is equalized. The writing operation and the equalizing operation are carried out in one clock cycle. Note that a write time of the first bit is shorter than those of the second bit and et seq., since an external address signal must be decoded to an internal address signal before writing of the first bit. This also applies to equalize circuit EQG and write buffer WB of bank #2.
FIG. 28 is a timing chart showing change of external signals and the potential of global IO line pair GIO at the time of random writing operation. In the random writing operation, address signal Add, a data signal, or the like are independently strobed whenever signal /CAS attains the L level, and data is written in memory cell MC at an address corresponding to each address signal Add. Also at the time of random writing operation, the writing operation and the equalizing operation are carried out in one clock cycle, similarly to the case of the continuous writing operation.
As described above, the SDRAM strobes external control signals ext./RAS, ext./CAS, address signal Add, a data signal, and the like at the rising edge of clock signal CLK for operation. Therefore, the SDRAM does not need to secure a data input/output margin taking a skew of an address or the like (offset of timing) into consideration, and the SDRAM can advantageously shorten a cycle time as compared to a conventional DRAM, which strobes an address or data in synchronization with external control signals ext./RAS and ext./CAS for operation. Further, in some systems in which several continuous bits are accessed at a high frequency, the average access time can be comparable to that of a static random access memory (SRAM) by increasing the speed of the continuous access operation.
FIG. 29 is a diagram functionally showing a structure of a main part of a conventional SDRAM of 2-bit prefetch. This figure is compared to FIG. 19. Since banks #1 and #2 have the same structure also in this SDRAM, only a part which is related to bank #1 will be described. For simplification of illustration, control signal generating circuit 62 and the like shown in FIG. 19 are omitted.
Referring to FIG. 29, in the SDRAM, a memory array 71a including global IO line pairs GIO and GIO' in two systems is provided in each functional block 400. Preamplifier group 55a and read register 56a are provided corresponding to one global IO line pair GIO, and a preamplifier group 55a' and read register 56a' are provided corresponding to the other global IO line pair GIO'. A selector 68a is provided for alternately applying each of outputs of two read registers 56a and 56a' to output buffer 57a. Selector 68a is controlled by a selector control signal .phi.SEr1 outputted from control signal generating circuit 63.
In addition, write register 59a and write buffer group 60a are provided corresponding to one global IO line pair GIO, and a write register 59a' and a write buffer group 60a' are provided corresponding to the other global IO line pair GIO'. A selector 69a is provided for applying the output of input buffer 58a to one of two write registers 59a and 59a' alternately. Selector 69a is controlled by a selector control signal .phi.SEw1 outputted from control signal generating circuit 63. An equalize circuit group 61a is provided in common to global IO line pairs GIO and GIO' in two systems.
FIG. 30 specifically shows arrangement of IO lines of the SDRAM shown in FIG. 29. This figure is compared to FIG. 21. In this SDRAM, two global IO line pairs GIO and GIO' are arranged along the longer side of memory mat MM, and two global IO line pairs GIO and GIO' are arranged in three word line shunt regions WS2, WS4 and WS6, respectively.
Two local IO line pairs LIO and LIO' are provided for connecting two global IO line pairs GIO and GIO' and selected 256-K bit memory array MA. Four local IO line pairs in total including two local IO line pairs LIO and LIO' arranged on one side and two local IO line pairs LIO and LIO' arranged on the other side are arranged for a single 256-K bit memory array MA. Two local IO line pairs LIO and LIO' are shared by two 256-K bit memory arrays MA adjacent to each other.
Block selecting switches BS are arranged for connecting global IO line pairs GIO and local IO line pairs LIO. Block selecting switches BS' are provided for connecting global IO line pairs GIO' and local IO line pairs LIO'. Two block selecting switches BS and BS' are arranged in an end portion of memory mat MM and three word line shunt regions WS2, WS4 and WS6.
FIG. 31 is a circuit block diagram showing a structure of a part which is related to one 32-K bit memory array MK with one part omitted. This figure is compared to FIG. 23. Referring to FIG. 31, in the SDRAM, two global IO line pairs GIO and GIO', two local IO line pairs LIO2 and LIO2', and two block selecting switches BS and BS' are provided as described above. Two local IO line pair equalize circuits EQL2 and EQL2' are provided corresponding to two local IO line pairs LIO2 and LIO2'.
One column selection line CSL is arranged corresponding to two bit line pairs BLP. Two bit line pairs BLP selected by one column selection signal CSL are connected to two local IO line pairs LIO2 and LIO2' through column selecting gate CSG2.
FIG. 32 is a circuit block diagram specifically showing a structure of a part which is related to writing operation of the SDRAM shown in FIG. 29. This figure is compared to FIG. 26.
Referring to FIG. 32, in the SDRAM, write buffer WB and equalize circuit EQG are provided corresponding to global IO line pair GIO, and write buffer WB' and equalize circuit EQG' are provided corresponding to global IO line pair GIO'. Write buffers WB and WB' are activated in response to signals .phi.WB1 and .phi.WB1', respectively. Equalize circuits EQG and EQG' are both activated in response to signal .phi.EQ1.
FIG. 33 is a timing chart showing continuous writing operation (burst length=4) of the circuit shown in FIG. 32. Referring to FIGS. 32 and 33, operation of the circuit of FIG. 32 will be described.
Data are divided between write registers 59a and 59a' according to a lower one bit of an address when a write command is inputted. In FIG. 33, the case where the lower address is "0" is shown. The first data is stored in write register 59a, and applied to global IO line pair GIO in response to signal .phi.WB1 attaining the H level in an active state. Data to be applied at the next rising edge of clock signal CLK is stored in write register 59a', and applied to global IO line pair GIO' in response to signal .phi.WB1' attaining the H level in an active state.
The data applied to global IO line pairs GIO and GIO' are written in two selected memory cells MC through corresponding local IO line pairs LIO and LIO' and two bit line pairs BLP. After writing is complete, signal .phi.EQ1 attains the H level in an active state, and two global IO line pairs GIO and GIO' are simultaneously equalized. Global IO line pairs GIO and GIO' are equalized every two clock cycles.
The advantage of the SDRAM of pipeline operation is that random writing on a bit basis can be carried out, since global IO line pair GIO is equalized whenever one bit of data is written, for preparation for the next data writing. More specifically, writing can be stopped and data can be written at a newly inputted address at timings shown by .smallcircle. marks in FIG. 27.
The SDRAM of pipeline operation has, however, a disadvantage that it is difficult to make an operating frequency higher, because it is necessary to change between the H and L levels the potential of an IO line having a large stray capacitance within one clock cycle for data writing.
On the other hand, the advantage of the SDRAM of 2-bit prefetch is that it is easy to make an operating frequency higher, because data is written every two clock cycles, which is twice longer than the case of the SDRAM of pipeline operation.
The SDRAM of 2-bit prefetch has, however, a disadvantage that random writing on a bit basis cannot be carried out, because an IO line is equalized every two clock cycles. More specifically, writing can be stopped and data can be written at a newly inputted address only at timings shown by .smallcircle. marks in FIG. 33. Therefore, the SDRAM of 2-bit prefetch cannot be used as a memory (for example, memory for image processing) which requires random writing operation on a 2-bit basis.
In other words, in the conventional SDRAM, random writing must be sacrificed for making the operating frequency higher. On the other hand, the high operating frequency must be sacrificed for random writing.